A new proposed eight bit hybrid mash-efm multi-order sigma delta modulator for audio dac

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dc.contributor.authorIjaz, Khalid
dc.date.accessioned2018-03-13T11:25:42Z
dc.date.available2018-03-13T11:25:42Z
dc.date.issued2016
dc.descriptionSupervised by: Dr. Muhammad Adnanen_US
dc.description.abstractDigital-to-Analog (DAC) Converters manifest a very imperative role in many applications where data is interfaced with real analog world. The occurrence of some problems like jitter, quantization errors, integral nonlinearity and conversion time reduces the performance of DAC. One of the most efficacious ways to combat these problems is the use of Sigma Delta Modulation (SDM) in DAC. This work emphasizes on the designing of Multi-order SDM to achieve high resolution DAC consuming low power and high SNR. The increase of oversampling ratio (OSR) requires the high speed DAC, overloads the quantizer, eventually reduces the DAC speed and increases the power consumption. Similarly, the complexity of the transistor circuitry in VLSI technology implementation increases as the order of SDM increases. Hybrid MASH-EFM architecture is used to overwhelm the above two conditions. MATLAB simulation will be used for comparison of different Multi-order SDM architectures to study the effect on DAC performance. Different performance parameters are recorded at different OSR’s of different architectures (MASH, EFM and Hybrid MASH-EFM).1st order Hybrid MASH-EFM SDM achieves high SNR equal to 131.7 db and ENOB of 16 bits at OSR of 5. These results reveal that the proposed architecture (Hybrid MASH-EFM) is superior to two existing architectures.en_US
dc.identifier.urihttps://escholar.umt.edu.pk/handle/123456789/2871
dc.language.isoenen_US
dc.publisherUniversity of Management and Technology Lahoreen_US
dc.subjectDigital-to-Analogen_US
dc.subjectSigma Delta Modulationen_US
dc.subjectMS Thesisen_US
dc.titleA new proposed eight bit hybrid mash-efm multi-order sigma delta modulator for audio dacen_US
dc.typeThesisen_US
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