Nano-CMOS spice level implementation of different modules for direct digital frequency synthesis application

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dc.contributor.authorHassan Muhuyuddin
dc.contributor.authorFaisal Yaseen
dc.contributor.authorMoazam Ali Khan
dc.contributor.authorRamsha Ayub
dc.date.accessioned2014-09-30T13:34:59Z
dc.date.available2014-09-30T13:34:59Z
dc.date.issued2014-07
dc.description.abstractIn this project we are implementing a ROM Less Direct Digital Frequency Synthesizer (DDFS).Direct Digital Frequency Synthesizer (DDFS) generates sinusoidal signals with desired controllable frequency. Most of the times sinusoidal information stored in the ROM . All ROM based solutions suffer from ROM intrinsic drawbacks, namely low speed, large area and high power consumption. Polynomial interpolation is used to eliminate the ROM in DDFS. Chebyshev fourth order polynomial is used to approximate the first quarter of cosine signal. The DDFS is implemented using Nano Cmos BSIM3 Model on LtSpice software and also implemented on Xilinx Vertex-II FPGA.en_US
dc.identifier.urihttps://escholar.umt.edu.pk/handle/123456789/1285
dc.language.isoenen_US
dc.publisherUniversity of Management and Technologyen_US
dc.subjectBS Thesisen_US
dc.subjectElectrical Engineeringen_US
dc.titleNano-CMOS spice level implementation of different modules for direct digital frequency synthesis applicationen_US
dc.typeThesisen_US
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