Browsing by Author "Abdul Aziz Bhatti"

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    Microcontroller based implementation of fuel cell and battery integrated hybrid power source
    (2012) Fahad Ali; Syed Mohsin Ali; Abdul Aziz Bhatti; Mashood Nasir
    This paper presents the implementation of a digitally controlled hybrid power source system, composed of fuel cell and battery. Use of individual fuel cell stacks as a power source, encounters many problems in achieving the desired load characteristics. A battery integrated, digitally controlled hybrid system is proposed for high pulse requirements. The proposed hybrid power source fulfils these peak demands with efficient flow of energy as compared to individual operations of fuel cell or battery system. A dc/dc converter is applied which provides an optimal control of power flow among fuel cell, battery and load. The proposed system efficiently overcomes the electrochemical constraints like over current, battery leakage current, and over and under voltage dips. By formulation of an intelligent algorithm and incorporating a digital technology (AVR Microcontroller), an efficient control is achieved over fuel cell current limit, battery charge, voltage and current. The hybrid power source is tested and analyzed by carrying out simulations using MATLAB simulink. Along with the attainment of desired complex load profiles, the proposed design can also be used for power enhancement and optimization for different capacities.
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    Reduced order multiport parallel and multidirectional neural associative memories
    (Biological Cybernetics, 2009) Abdul Aziz Bhatti
    This paper proposes multiport parallel and multidirectional intraconnected associative memories of outer product type with reduced interconnections. Some new reduced order memory architectures such as k-directional and k-port parallel memories are suggested. These architectures are, also, very suitable for implementation of spatiotemporal sequences and multiassociative memories. It is shown that in the proposed memory architectures, a substational reduction in interconnections is achieved if the actual length of original N-bit long vectors is subdivided into k sublengths. Using these sublengths, submemory matrices, Ts or Ws , are computed, which are then intraconnected to form k-port parallel or k-directional memories. The subdivisions of N-bit long vectors into k sublengths save (k−1)×100 k % of interconnections. It is shown, by means of an example, that more than 80% reduction in interconnections is achieved. Minimum limit in bits on k as well as maximum limit on subdivisions in k is determined. The topologies of reduced interconnectivity developed in this paper are symmetric in structure and can be used to scale up to larger systems. The underlying principal of construction, storage and retrieval processes of such associative memories has been analyzed. The effect of complexity of different levels of reduced interconnectivity on the quality of retrieval, signal to noise ratio, and storage capacity has been investigated. The model possesses analogies to biological neural structures and digital parallel port memories commonly used in parallel and multiprocessing systems.