Abdullah AizazdodhyWaqar ShahzadAbad Ul Hassan2016-04-122016-04-122015https://escholar.umt.edu.pk/handle/123456789/1726Advisor: Mr. Mohammad Asim ButtThis thesis is basically the implementation of quadrature direct digital frequency synthesizer (QDDFS) which is one of the main building blocks used in software defined radios (SDR). The implementation of the DDFS computes the sine and cosine function on a single edge of the clock, proving it to be optimized in terms of area and speed. The actual architecture which can be offered in the papers is better than CO-ordinate Rotation Digital Computer (CORDIC) as well as Singleton's offered architecture. Complete designing procedure is explained in the report for better understanding the operation of Direct Digital Frequency Synthesizer. All the computations are performed using Q m.n fixed number representation system. Fixed-Point implementation was accomplished using ModelSim simulator. Verilog HDL is a Hardware descriptive language and is used as a description language to map different algorithms. Artix-7 Field Programmable Gate Array (FPGA) Nexys-4 by Digilent is chosen as a Hardware Platform for the System Implementation.BS ThesisQuadratureQuadrature direct digital frequency synthesizerField Programmable Gate ArrayThesis