Syed Rehan TariqNafees TaimoorAbdullah MehmoodWaseem Abbas2013-04-012013-04-012012https://escholar.umt.edu.pk/handle/123456789/735Project Advisor: Sir Muhammad BilalComputer organization and design is a common engineering course where students learn concepts of modern computer architecture. Students often learn computer design by implementing individual sections of a computer microprocessor using a simulation only approach that limits a student's experience to software design. This project targets the computer architecture courses and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor via verilog design. The goal of this project is to enhance the simulator based approach by integrating some hardware design to help the computer architecture students gain a hands-on experience in hardware-software integration and achieve a better understanding of both the MIPS single-cycle and pipelined processors as described in the widely used book.enComputer architectureRISC(Reduced Instruction Set Computer)BS ThesisCommon EngineeringMIPS(Microprocessor without Interlocked Pipeline Stages)FPGA (Field programmable gate arrays)Thesis