Nano-CMOS spice level implementation of different modules for direct digital frequency synthesis application

Abstract

In this project we are implementing a ROM Less Direct Digital Frequency Synthesizer (DDFS).Direct Digital Frequency Synthesizer (DDFS) generates sinusoidal signals with desired controllable frequency. Most of the times sinusoidal information stored in the ROM . All ROM based solutions suffer from ROM intrinsic drawbacks, namely low speed, large area and high power consumption. Polynomial interpolation is used to eliminate the ROM in DDFS. Chebyshev fourth order polynomial is used to approximate the first quarter of cosine signal. The DDFS is implemented using Nano Cmos BSIM3 Model on LtSpice software and also implemented on Xilinx Vertex-II FPGA.